1. Field of the Invention
The present invention relates to a semiconductor memory device that has a plurality of memory-cell arrays composed of a DRAM or the like within a memory chip, and particularly relates to an address-system circuit within the memory chip.
2. Description of the Related Art
Conventionally, in a semiconductor memory device of the bank switching method wherein a plurality of memory banks are built into a memory chip and used by switching, an address-latch circuit section that latches address data input from the outside to output the latched address data into each memory bank has been collectively arranged at a central part of the memory.
FIG. 5 is a schematic block diagram that illustrates an exemplary construction of such a semiconductor memory device of the bank switching method and shows an example of arranging the components within a memory chip. In FIG. 5, the case where 4 memory banks are owned is shown as an example.
In FIG. 5, an address signal (hereafter called external address signal) EADD input from an external system device 110, which controls the operation of a semiconductor memory device 100, is input to an address-input buffer section 101. An internal address signal IADD is generated in the address-input buffer section 101. The output internal address signal IADD is latched in an address-latch circuit section 102 and output to each memory bank 103 to 106 from that address-latch circuit section 102 as an address-latch signal ADDL.
In the following, an example is described, in which the address signals are composed as follows. The external address signal EADD is composed of 15-bit address data consisting of 2-bit bank-address data EBA[0-1] and the subsequent 13-bit address data EA[0-12]. The internal address signal IADD is composed of 15-bit address data consisting of 2-bit bank-address data IBA[0-1] and the subsequent 13-bit address data IA[0-12]. Further, in the example, the address-latch signal ADDL is composed of 15-bit address data consisting of 2-bit bank-address data BAL[0-1] and the subsequent 13-bit address data AL[0-12].
The [0-12] in the address data EA[0-12], IA[0-12], and AL[0-12] indicates a 13-bit data unit consisting of the 0th to 12th bits, and similarly, [0-1] in the bank-address data EBA[0-1], IBA[0-1], and BAL[0-1] indicates a 2-bit data unit consisting of the 0th to 1st bits.
As shown in FIG. 5, conventionally, the address-latch circuit section 102 has been arranged at a central part of a memory chip 107. However, if the address-input buffer section 101 is arranged away from a central part of the memory chip 107, wiring for transmitting the internal address signal IADD from the address-input buffer section 101 to the address-latch circuit section 102 becomes long, so that there has been a case where the setup/hold characteristics for addresses become worse owing to coupling noise between the wiring lines and the like.
On the other hand, FIG. 6 shows the wiring lines on which the internal address signal IADD is transmitted, i.e., signal lines SL0 to SL14 on which the corresponding bits of the bank-address data IBA[0-1] and address data IA[0-12] are respectively transmitted. FIG. 6 also shows parasitic capacitance formed between each pair of adjacent signal lines. Paying attention to the signal line SL1 on which the address bit data 1A[1] is transmitted in FIG. 6, we now describe the setup/hold characteristics of addresses, referring to the timing chart in FIG. 7.
The setup/hold time for addresses is the setup/hold time for the external address signal EADD corresponding to an external clock signal ECLK. In the semiconductor memory device 100, the setup/hold time for addresses is determined by the timing of internal address signal IAD from the address-input buffer section 101 and rises in an internal clock ICLK.
First, the case where the address bit data IA[1] changes from low level to high level is explained. In this case, the address bit data IA[0] and IA[2] on the signal lines SL0 and SL2 adjacent to the signal line SL1, i.e., the address data IA[0,2], can be at the three transient states: state a of no change, rising state b from low to high level, and falling state c from high to low level. We now describe the setup/hold characteristics of the address data IA[1] at the b and c state on the basis of the a state.
In FIG. 7, the address data IA[1] and IA[0,2] at the a state are respectively indicated by IA[1]a and IA[0,2]a. Similarly, the address data IA[1] and IA[0,2] at the b state are respectively indicated by IA[1]b and IA[0,2]b, and the address data IA[1] and IA[0,2] at the c state are respectively indicated by IA[1]c and IA[0,2]c. Also, in FIG. 7, the setup time tS and the hold time tH at the a state are respectively indicated by tSa and tHa, the setup time tS and the hold time tH at the b state are respectively indicated by tSb and tHb, and the setup time tS and the hold time tH at the c state are respectively indicated by tSc and tHc.
At the b state, the address data IA[1] and IA[0,2] vary with the same phase. Therefore, coupling noise between wiring lines, i.e. interference by signals on adjacent lines through parasitic capacitance formed between wiring lines occurs, so that the address data IA[1] rises faster than at the a state.
Next, at the c state, the address data IA[0,2] varies with a phase inverse to that of IA[1]. Therefore, coupling noise between wiring lines occurs, so that the address data IA[1] rises slower than at the a state.
Now, we compare the effects of the b state and the c state on the address data IA[1]. The setup time tS and the hold time tH for the address data EA[1], which is the first bit data of the external address signal EADD, corresponding to the external clock signal ECLK, are the same. However, the setup time and hold time corresponding to the internal clock signal ICLK in the address-latch circuit section 102, which determine the setup/hold characteristics for the addresses, become different. Therefore, the setup time and hold time for addresses become dispersed corresponding to the changes in the address data of the adjacent signal lines.
In this way, if the signal lines SL0 to SL14 on which the internal address signal IADD is transmitted become longer, setup time and hold time for addresses become dispersed by coupling noise between adjacent signal lines, so that there have been cases where the setup/hold characteristics for addresses deteriorate.
The object of the present invention is to solve the aforementioned problem and to provide a semiconductor memory device that can reduce the dispersion of setup time and hold time for addresses due to coupling noise and can improve the setup/hold characteristics for addresses by arranging the address-latch circuit section on the memory chip so that wiring between the input buffer section and the address-latch circuit section becomes short.
A semiconductor memory in accordance with the present invention is equipped with a memory section that is composed of a plurality of memory banks, an address-input buffer section that generates and outputs an internal address signal corresponding to an external address signal, which is an address signal input from the outside, a first address-latch circuit section that latches data indicative of a desired memory bank contained in the internal address signal output from the address-input buffer section to output to each memory bank of the above memory section, and a second address-latch circuit section that latches data indicative of a cell address contained in the internal address signal output from the address-input buffer section to output to each memory bank of the above memory section, the second address-latch circuit section being arranged at a neighborhood of the address-input buffer section. In this way, the second address-latch circuit section is arranged at a neighborhood of the address-input buffer section, so that the effects of coupling noise between the wiring lines on which corresponding predetermined address data of the internal address signal are transmitted can be reduced. Therefore, the dispersion of setup time and hold time for addresses is reduced, and the setup/hold characteristics for addresses can be improved.
The above first address-latch circuit section further latches data contained in the internal address signal that is used for generating commands for performing the operation control of each memory bank of the memory section, and outputs the latched address data into each memory bank of the memory. Therefore, delays in a control signal for each memory bank can be prevented.
Also, the address-input buffer section is arranged at a terminal part of the memory chip, and the first address-latch circuit section is arranged at a central part of the memory chip. By this means, wiring for transmitting predetermined address data in the internal address signal between the address-input buffer section and a central part of the memory chip becomes unnecessary, so that design efficiency in the pattern layout can be improved.
On the other hand, the address-input buffer section may be composed of a plurality of address-input buffers, and the second address-latch circuit section may be composed of a plurality of address-latch circuits respectively built corresponding to the address-input buffers, and each address-latch, circuit may be arranged at a neighborhood of the corresponding address-input buffer. By this means, when the address-input buffer section consists of a plurality of decentralized address-input buffers, the effects of coupling noise between the wiring lines on which predetermined address data in the internal address signal are transmitted can be reduced, and the dispersion of setup time and hold time for addresses can be reduced, so that the setup/hold characteristics for addresses can be improved.
Specifically, each address-input buffer generates and outputs address data, which is part of an internal address signal, depending on the corresponding address data in the input external address signal. Then each address-latch circuit latches predetermined address data in the input address signal output from the corresponding address-input buffer and outputs into each memory bank in the memory section. By this means, if the address-input buffer consists of a plurality of decentralized address-input buffers, delays in a control signal for each memory bank can be prevented.
Further, each address-input buffer may be arranged at a terminal part of the memory chip. By this means, if the address-input buffer section consists of a plurality of decentralized address-input buffers, wiring for transmitting predetermined address data in the internal address signal between each address-input buffer and a central part of the memory chip becomes unnecessary, so that design efficiency in the pattern layout can be improved.